A 56−67 GHz Low-Noise Amplifier with 5.1-dB NF and 2.5-kV HBM ESD Protection in 65-nm CMOS

This paper presents a V-band low-noise amplifier with high RF performance and ESD robustness. An inductortriggered silicon-controlled rectifier (SCR) assisted with both a PMOS and an inductor is proposed to enhance the ESD robustness and minimize the impact of the ESD protection block on the millimeter-wave LNA. The initial-on PMOS improves the turn-on speed and the inductor resonates with the parasitic capacitance, respectively. Also, a 3-stage wideband V-band LNA is designed by using the gate inductor in the common-gate stage of the cascode topology as gain peaking to compensate the roll-off at high frequencies for bandwidth extension. The measured results demonstrate a 2.5-kV HBM ESD protection level with a minimum noise figure (NF) of 5.1 dB and a peak gain of 22 dB , also a 3-dB bandwidth of 56−67 GHz can be achieved under a power consumption of only 23 mW. Index Terms —CMOS, electrostatic discharge (ESD), low-noise amplifier (LNA), and millimeter wave (mm-Wave).